Timing mechanisms in computers of the current art typically conform generally to the architecture and topology depicted in FIG. 1. High-speed clock 101 (typically generating ticks in microseconds or nanoseconds) feeds prescaler 102, whose ports 103 scale down increments of raw clock ticks to increasingly coarser intervals. In the example of FIG. 1, successive ports 103.sub.1 through 103.sub.n scale down increments of raw clock ticks to selected intervals increasing by some power of two (in the case of FIG. 1, intervals of 2.sup.3, or 8).
Timing operations are then enabled by placing values in registers R. The actual values represent numbers from which the mechanism counts down to zero. When zero is reached from a desired value, a processor interrupt is generated.
Select mux 104 selects the prescaler port 103 whose interval will dictate the rate at which raw counting takes place in register R. The time until processor interrupt for a particular selected value in R is thus the time to count down to zero from that value in R at the interval corresponding to the particular prescaler port 103 selected by mux 104.
With further reference to the current art example of FIG. 1, recurring values (to generate a series of equidistant timed events) are optionally placed into registers R via phantom registers P. Instead of counting down to zero each time from a separate new value, a recurring value is loaded once into the phantom register P corresponding to R.
Then, as R reaches zero, a processor interrupt occurs, whereupon phantom register P reinitializes R for a further recurring counting cycle.
A further feature of the current art as illustrated in FIG. 1 is the optional capability to concatenate registers R.sub.1 and R.sub.2 when additional length is required to count down from a number exceeding the capacity of original register R. This situation typically arises when it is desired to time a fairly long event at a relatively fine counting interval on prescaler 102, where the value to be counted from exceeds the capacity of register R.sub.1. In such cases, the prior art as illustrated in FIG. 1 may optionally provide selector 105, where register R.sub.2 can be temporarily concatenated with register R.sub.1. When not required, selector 105 re-establishes register R.sub.2 's connection to mux 104 so that R.sub.2 can perform timing operations independently.
Current art timing mechanisms such as the one illustrated in FIG. 1 are primarily useful when the system requires the same interval to be timed repeatedly. For example, the mechanism of FIG. 1 lends itself to timing the system's "heartbeat" interval. The heartbeat value to be repeated is loaded into phantom register P just once, at which point the mechanism times sequential intervals corresponding to that value.
A problem arises, however, if it is desired to time multiple irregular intervals concurrently. The advantage of repetition via phantom register P is lost. Multiple individual timing mechanisms become necessary, one for each irregular interval to be timed. A computer in which many events are occurring on asynchronously or irregularly timed cycles will thus require an inordinate amount of hardware devoted to this activity. While it is possible to time two or more asynchronous events off one register, this must be done by calculating intervening "delta" values to enable processor interrupts at the correct time. This generates unnecessary processing overhead.
Some current systems compromise by trying to do timing as much as possible off the heartbeat. This will be readily seen to be disadvantageous. The available timing resolution is immediately coarsened to the heartbeat interval. Accelerating the heartbeat interval to improve resolution generates a geometric increase in processing overhead.
Another disadvantage of current art timing systems such as described with reference to FIG. 1 is that in selecting a register R to load to a value of V, a compromise must be made of timing resolution against size of register that can hold the actual value of V. If a long period is required to be timed with a high degree of accuracy, then a large value of V will be required to be loaded in a register R whose prescaler port 103 counts down with fine resolution. When multiple timing mechanisms are used for timing multiple long timing intervals with a high resolution, then multiple large registers are required. At some point, even with the capability to concatenate registers, hardware constraints place a limit on the size of the multiple large registers that will in turn limit the size of value V that can be loaded. This places an upper limit of time interval that can be timed to that degree of accuracy.
There is therefore a need in the art for an irregular interval timer that may measure multiple irregular or asynchronous intervals concurrently and still require comparatively little hardware in deployment. Ideally, the amount of hardware available should not be a practical limitation on the number of events that may be timed concurrently. Also, there should not be a hardware-imposed practical limitation on the length of a time period that may be timed at a high level of resolution.